An erasable and programmable non-volatile memory, such as an EPROM, is typically formed as an integrated circuit and comprises an array of memory cells, means for selecting these cells, as well as means to program and read them. The cells of the array are organized in a matrix of columns and rows. The memory cells of one and the same column are connected to a bit line, and the memory cells of one and the same row are connected to a word line. The memory cells may be in a programmed state in which they pass an electrical current, or in an erased state in which they oppose the passage of this current.
Each memory cell includes a selection transistor and a floating-gate transistor. The information on the state of the memory cell is determined via a trapped charge stored in the floating-gate transistor. Thus, the memory cell is erased if a floating gate of the corresponding transistor is charged with electrons. Conversely, the memory cell is programmed if the floating gate is depleted of electrons. The charging and discharging of the floating gate is obtained by applying a high voltage to the gate or drain of the floating-gate transistor of the memory cell to be written in. This high voltage, in a range of about 15-20 volts, is provided by a high-voltage generator.
A simplified drawing of a prior art EEPROM is shown in FIG. 1. For the sake of clarity, this drawing has only one memory cell CM. This cell has a selection transistor TS and a floating-gate transistor TGF series-connected between a bit line LB and ground. The gate of the selection transistor TS is connected to a word line LM, while the drain is connected to the bit line LB.
The selection of the memory cell is done by means of a row decoder DL and a column decoder DC. These decoders decode the address signals A1, A2, A3, A4 and A5. The row decoder DL enables the selection of a word line, such as the word line LM. The column decoder DC enables the connection of the bit line LB to a pin P1 or to a read circuit CL by means of a transistor T1. The pin P1 receives a voltage signal Vp1. These decoders DC and DL also control two other transistors, T2 and T3 respectively, which are series-connected between a pin P2 and the gate of the floating-gate transistor TGF. A voltage signal Vp2 is applied to the pin P2. These transistors are designed to provide the voltage signal Vp2 to the gate of the transistor TGF. Furthermore, the decoders DC and DL are supplied by a voltage signal Vpp provided by a voltage ramp generator. In the following description, the references VLM, V2 and V1 designate the voltage signals respectively applied to the word line LM, to the gate, and to the drain of the floating-gate transistor TGF.
A write operation in an EEPROM memory conventionally requires an erasure cycle and a programming cycle. The erasure cycle performs a zero-setting (or an erasure) of all the cells of the word to be written and the programming cycle performs a one-setting of the cells corresponding to the non-zero bits of the word to be written.
A write operation in the memory cell CM is illustrated by the timing diagrams of the signals vpp, VLM, Vp2 and Vp1 shown in FIGS. 2a through 2d. In a first phase (erasure cycle) the cell CM is erased, and in a second phase (programming cycle) the cell CM is programmed. At each cycle, the ramp generator is put into operation and generates the voltage signal Vpp as shown in FIG. 2a. The voltage signal Vpp has a rising phase during which the voltage climbs from a reference voltage up to a voltage plateau Vh. During the voltage plateau, the voltage is held at this level. The voltage signal Vpp has a decreasing phase when the voltage returns to its reference value. Since the signals VLM, Vp2, Vp1 are derived from the signal Vpp, they have the same shape as the signal Vpp when they are not at a zero level. The initial reference voltage of the signal Vpp is equal to the supply voltage of the memory (about 5 volts), whereas it is zero for the signals VLM, Vp2 and Vp1. Furthermore, the plateau of these signals is at a voltage typically equal to 18 volts. The voltage signals Vp1 and Vp2 are set at zero respectively during the erasure cycle and the programming cycle.
FIGS. 2e and 2f show the timing diagrams of the voltages V2 and V1 respectively applied to the gate and drain of the transistor TGF during a write operation. These timing diagrams are nearly identical to the timing diagrams of the signals Vp2 and Vp1, except for two differences: 1) the maximum voltage of the signals V2 and V1 (about 16 volts) is slightly smaller than that of the signals Vp2 and Vp1, with a small loss in voltage occurring at the terminals of the selection transistors T1, T2, T3 and TS; and 2) the return to the reference voltage is slower due to the high capacitive load of the selection transistors T3 and TS.
A slow discharge of the transistors T3 and TS may weaken them and cause deterioration. While the gate potential of the transistor TS or T3 goes from about 18 volts to 0 volts, the source potential falls by only a few volts, from about 16 volts to 10 volts.
As a result of the slow discharge of transistor T3 or TS, and the level of change in voltage potentials to the gate and the source, two phenomena occur. First, the difference in potential between the gate electrode and the source electrode of the transistor T3 in the event of erasure (or of the transistor TS in the event of programming) changes polarity from +2 volts to -10 volts, and then falls back to 0 volts. The crossing of the potentials then prompts an injection of hot electrons into the gate oxide of this transistor. The second phenomenon occurs at the end of the drop in voltage VLM (equal to a few volts). The voltage applied to the drain of the transistor T3 (or TS) remains high, and an avalanche effect occurs at the drain of this transistor, thus prompting a high substrate current.
These two phenomena tend to weaken the gate oxide layer of the selection transistors. Since the EEPROM type memories are generally required to undergo a very large number of write cycles, this raises a problem of reliability with respect to the memory.